Verification Engineer
Stellent IT LLC
- Job
- 28388
- Posted
- Location
- San Jose, CA
- Work type
- Full Time
- Tax terms
- W2, Yearly
- Experience
- Experience open
- Openings
- 1 opening
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Skills
- Python
- C++
- Requirements
About the job
Hello,
Title :: Verification Engineer
Location :: San Jose, CA
Job Type- Fulltime
Below is the job description ::
- Test bench development using System Verilog UVM.
- Test plan and test case development with functional coverage, assertion, coverage property, coverage groups and coverage collections.
Requirements:
- 10+ Design Verification experience.
- Deep knowledge about System Verilog, UVM and verification coverage matrix.
- Strong experience with PCIe.
- Very familiar with the peripheral protocols such as UART, I2C, SPI Flash.
- Proficient in Python or Perl scripting.
- Programming experience with C/C++.
Best Regards,
Ishika
SR. IT Technical/Engineer Recruiter
Ph No-
Email:
Address: 505 Knolle Court, Saint Augustine, FL 32092