Physical Design Engineer
dBestWorkz LLC
- Job
- 34954
- Posted
- Location
- Palo Alto, CA
- Work type
- Contract
- Tax terms
- W2, C2C, 1099
- Experience
- Experience open
- Openings
- 1 opening
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Skills
- Tsmc
- 2NP
- 3NP
- DRC
- LVS
- ERC
About the job
Location : Palo Alto, CA (Full Onsite)
· Exposure to TSMC 2NP/3NP is must
· Perform endtoend physical design flow:
o Floorplanning
o Power planning (PG grid, IR)
o Placement & optimization
o CTS (Clock Tree Synthesis)
o Routing
o Postroute optimization
· Achieve timing closure across all modes and corners
· Resolve DRC, LVS, ERC and signoff violations
· Handle lowpower design techniques:
o MultiVt, Multivoltage (UPF)
o Power gating, clock gating
· Perform physical verification and signoff:
o STA (Primetime)
o SI / Crosstalk
o IR drop & EM analysis
· Work on advanced nodes (7nm, 5nm, 3nm or below)
· Collaborate with:
o RTL & Microarchitecture teams
o DFT & Test engineers
o Foundry and CAD teams
· Debug complex timing, congestion, power, and variability issues
· Drive methodology improvements and automation (scripts/flows)