Physical Design Engineer - Lead
Apetan Consulting
- Job
- 34972
- Posted
- Location
- San Jose, CA
- Work type
- Full Time
- Tax terms
- W2, Yearly
- Experience
- Experience open
- Openings
- 1 opening
Opens your email app with a message to the employer, its subject naming this job. Attach your resume and send it from your own email.
Skills
- Physical Design
- Emir
- LEC
- Vclp
- Static Timing Analysis
- Clock Tree Synthesis
- Place & Route
- Asic
About the job
Position: Physical Design Engineer - Lead
Locations: San Jose, San Diego, Irvine, CA (Onsite)
What You Will Do:
- Drive ASIC physical design implementation from floorplanning through signoff.
- Perform Place & Route (PnR), Clock Tree Synthesis (CTS), timing closure, and optimization.
- Achieve Power, Performance, and Area (PPA) targets.
- Develop and validate timing constraints and perform Static Timing Analysis (STA).
- Execute LEC, VCLP, and EMIR signoff activities.
- Collaborate with cross-functional teams to resolve implementation and timing challenges.
Required Skills:
- Strong experience in ASIC Physical Design.
- Hands-on expertise in:
- Floorplanning
- PnR
- CTS
- Timing Closure & STA
- Timing Constraints
- PPA Optimization
- LEC
- VCLP
- EMIR
- Ability to independently drive design closure and solve complex implementation issues.
Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Experience with advanced-node ASIC/SoC designs is preferred.